TI DSP TMS320F280025 Note17：CMPSS原理与使用

TMS320F280025 模数转换器(ADC)

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CMPSS框图

所谓比较器，正端输入大于负端输入时，输出高；正端输入小于负端输入时，输出低
负端输入通过设置寄存器可选则对应接口，或者内部参考
内部参考可选择是DACHVALS还是斜坡发生器
内部参考电压VDDA或VDAC
负端输入电压为： 内部参考电压 * DACHVALS / 4096
比较器输出可以直接作为CMPSS输出输出，也可以进行滤波/同步再输出
CMPSS模块只是输出一个高或低的信号，这个信号都是通过XBAR模块传输到其他外设的

比较器参考

内部参考电压VDDA或VDAC
负端输入电压为： 内部参考电压 * DACHVALS / 4096

斜坡发生器

斜坡发送器能让我们的比较器负端输入递减，实现特定需求的功能

滤波器

滤波器其实就是if else功能

比较器应用

CMPSSDriver.c

/** CMPSSDriver.c**  Created on: 2024年8月13日*      Author: Paranoid*/
#include "main.h"void CMPSS1Driver_Init(void)
{EALLOW;//// Analog PinMux for A2/C9// AIO -> Analog mode selectedGpioCtrlRegs.GPHGMUX1.bit.GPIO224 = 0;GpioCtrlRegs.GPHMUX1.bit.GPIO224 = 0;GpioCtrlRegs.GPHINV.bit.GPIO224 = 0;GpioCtrlRegs.GPHAMSEL.bit.GPIO224 = 1;EDIS;EALLOW;//// Select the value for CMP1HPMXSEL./Select the value for CMP1LPMXSEL.//AnalogSubsysRegs.CMPHPMXSEL.bit.CMP1HPMXSEL = 0;AnalogSubsysRegs.CMPLPMXSEL.bit.CMP1LPMXSEL = 0;EDIS;EALLOW;//// Sets the configuration for the high comparator.// Sets the configuration for the low comparator.Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = 0;Cmpss1Regs.COMPCTL.bit.COMPHINV = 0;Cmpss1Regs.COMPCTL.bit.ASYNCHEN = 0;Cmpss1Regs.COMPCTL.bit.COMPLSOURCE = 0;Cmpss1Regs.COMPCTL.bit.COMPLINV = 0;Cmpss1Regs.COMPCTL.bit.ASYNCLEN = 0;EDIS;//// Sets the configuration for the internal comparator DACs.EALLOW;Cmpss1Regs.COMPDACCTL.bit.SWLOADSEL = 0;Cmpss1Regs.COMPDACCTL.bit.SELREF = 0;Cmpss1Regs.COMPDACCTL.bit.DACSOURCE = 0;EDIS;//// Sets the value of the internal DAC of the high comparator.//Sets the value of the internal DAC of the low comparator.EALLOW;Cmpss1Regs.DACHVALS.bit.DACVAL = 2048U;Cmpss1Regs.DACLVALS.bit.DACVAL = 0U;EDIS;////  Configures the digital filter of the high comparator.//EALLOW;Cmpss1Regs.CTRIPHFILCTL.bit.SAMPWIN = 0;Cmpss1Regs.CTRIPHFILCTL.bit.THRESH = 0;Cmpss1Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 0;EDIS;//// Configures the digital filter of the low comparator.//EALLOW;Cmpss1Regs.CTRIPLFILCTL.bit.SAMPWIN = 0;Cmpss1Regs.CTRIPLFILCTL.bit.THRESH = 0;Cmpss1Regs.CTRIPLFILCLKCTL.bit.CLKPRESCALE = 0;EDIS;//// Sets the output signal configuration for the high comparator.//EALLOW;Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = 0;Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = 0;EDIS;//// Sets the output signal configuration for the low comparator.//Cmpss1Regs.COMPCTL.bit.CTRIPOUTLSEL = 0;Cmpss1Regs.COMPCTL.bit.CTRIPLSEL = 0;EDIS;//// Sets the comparator hysteresis settings.//EALLOW;Cmpss1Regs.COMPHYSCTL.bit.COMPHYS = 0U;EDIS;//// Configures the comparator subsystem's ramp generator.//EALLOW;Cmpss1Regs.COMPDACCTL.bit.RAMPSOURCE = 0;Cmpss1Regs.COMPDACCTL.bit.RAMPLOADSEL = 1;Cmpss1Regs.RAMPMAXREFS = 0;Cmpss1Regs.RAMPDECVALS = 0;Cmpss1Regs.RAMPDLYS.bit.DELAY = 0;EDIS;//// Disables reset of HIGH comparator digital filter output latch on PWMSYNC// Disables reset of LOW comparator digital filter output latch on PWMSYNCEALLOW;Cmpss1Regs.COMPSTSCLR.bit.HSYNCCLREN = 0;Cmpss1Regs.COMPSTSCLR.bit.LSYNCCLREN = 0;EDIS;//// Sets the ePWM module blanking signal that holds trip in reset.// Disables an ePWM blanking signal from holding trip in reset.EALLOW;Cmpss1Regs.COMPDACCTL.bit.BLANKSOURCE = 0;Cmpss1Regs.COMPDACCTL.bit.BLANKEN = 0;EDIS;//// Configures whether or not the digital filter latches are reset by PWMSYNC//EALLOW;Cmpss1Regs.COMPSTSCLR.bit.HSYNCCLREN = 0;Cmpss1Regs.COMPSTSCLR.bit.LSYNCCLREN = 0;EDIS;//// Enables the CMPSS module.//EALLOW;Cmpss1Regs.COMPCTL.bit.COMPDACE = 1;EDIS;//// Delay for CMPSS DAC to power up.//DEVICE_DELAY_US(500);EALLOW;GpioCtrlRegs.GPAGMUX2.bit.GPIO24 = 0;GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1;EDIS;EALLOW;OutputXbarRegs.OUTPUTLATCHENABLE.bit.OUTPUT1 = 0;OutputXbarRegs.OUTPUTINV.bit.OUTPUT1 = 0;////Mux configuration//OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX0 = 1;EDIS;}void CMPSS2Driver_Init(void)
{// Analog PinMux for A10/c10// AIO -> Analog mode selectedEALLOW;GpioCtrlRegs.GPHGMUX1.bit.GPIO230 = 0;GpioCtrlRegs.GPHMUX1.bit.GPIO230 = 0;GpioCtrlRegs.GPHINV.bit.GPIO230 = 0;GpioCtrlRegs.GPHAMSEL.bit.GPIO230 = 1;EDIS;//// Select the value for CMP1HPMXSEL./Select the value for CMP1LPMXSEL.//EALLOW;AnalogSubsysRegs.CMPHPMXSEL.bit.CMP2HPMXSEL = 3;AnalogSubsysRegs.CMPLPMXSEL.bit.CMP2LPMXSEL = 3;AnalogSubsysRegs.CMPHNMXSEL.bit.CMP2HNMXSEL = 0;AnalogSubsysRegs.CMPLNMXSEL.bit.CMP2LNMXSEL = 0;
//    AnalogSubsysRegs.LOCK.bit.VREGCTL = 1;EDIS;//// Sets the configuration for the high comparator.// Sets the configuration for the low comparator.EALLOW;Cmpss2Regs.COMPCTL.bit.COMPHSOURCE = 0;Cmpss2Regs.COMPCTL.bit.COMPHINV = 0;Cmpss2Regs.COMPCTL.bit.ASYNCHEN = 0;Cmpss2Regs.COMPCTL.bit.COMPLSOURCE = 0;Cmpss2Regs.COMPCTL.bit.COMPLINV = 0;Cmpss2Regs.COMPCTL.bit.ASYNCLEN = 0;EDIS;//// Sets the configuration for the internal comparator DACs.EALLOW;Cmpss2Regs.COMPDACCTL.bit.SWLOADSEL = 0;Cmpss2Regs.COMPDACCTL.bit.SELREF = 0;Cmpss2Regs.COMPDACCTL.bit.DACSOURCE = 0;EDIS;//// Sets the value of the internal DAC of the high comparator.//Sets the value of the internal DAC of the low comparator.EALLOW;Cmpss2Regs.DACHVALS.bit.DACVAL = 2048U;Cmpss2Regs.DACLVALS.bit.DACVAL = 0U;EDIS;////  Configures the digital filter of the high comparator.//EALLOW;Cmpss2Regs.CTRIPHFILCTL.bit.SAMPWIN = 0;Cmpss2Regs.CTRIPHFILCTL.bit.THRESH = 0;Cmpss2Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 0;EDIS;//// Configures the digital filter of the low comparator.//EALLOW;Cmpss2Regs.CTRIPLFILCTL.bit.SAMPWIN = 0;Cmpss2Regs.CTRIPLFILCTL.bit.THRESH = 0;Cmpss2Regs.CTRIPLFILCLKCTL.bit.CLKPRESCALE = 0;EDIS;//// Sets the output signal configuration for the high comparator.//EALLOW;Cmpss2Regs.COMPCTL.bit.CTRIPOUTHSEL = 0;Cmpss2Regs