Verilog刷题笔记62

题目:
Exams/review2015 fancytimer
This is the fifth component in a series of five exercises that builds a complex counter out of several smaller circuits. You may wish to do the four previous exercises first (counter, sequence recognizer FSM, FSM delay, and combined FSM).

解题:

module top_module (input clk,input reset,      // Synchronous resetinput data,output [3:0] count,output counting,output done,input ack );parameter s0=0,s1=1,s11=2,s110=3,s1101=4,b1=5,b2=6,b3=7,cnt=8,waitter=9;reg [3:0]state,next_state;reg [15:0]counter;reg [3:0]delay,delay0;always@(posedge clk)beginif(reset)state=s0;elsestate=next_state;endalways@(*)begincase(state)s0:next_state=data?s1:s0;s1:next_state=data?s11:s0;s11:next_state=data?s11:s110;s110:next_state=data?s1101:s0;s1101:next_state=b1;b1:next_state=b2;b2:next_state=b3;b3:next_state=cnt;cnt:next_state=(counter==(delay0+1)*1000-1)?waitter:cnt;waitter:next_state=ack?s0:waitter;endcaseendalways@(posedge clk)begincase(state)s1101:delay[3:0]={delay[2:0],data};b1:delay[3:0]={delay[2:0],data};b2:delay[3:0]={delay[2:0],data};b3:begin delay[3:0]={delay[2:0],data};delay0=delay;endcnt:begin counter=counter+1;if(counter==1000)delay=delay-1;else if(counter==2000)delay=delay-1;else if(counter==3000)delay=delay-1;else if(counter==4000)delay=delay-1;else if(counter==5000)delay=delay-1;else if(counter==6000)delay=delay-1;else if(counter==7000)delay=delay-1;else if(counter==8000)delay=delay-1;else if(counter==9000)delay=delay-1;else if(counter==10000)delay=delay-1;else if(counter==11000)delay=delay-1;else if(counter==12000)delay=delay-1;else if(counter==13000)delay=delay-1;else if(counter==14000)delay=delay-1;else if(counter==15000)delay=delay-1;else if(counter==16000)delay=delay-1;enddefault:begin counter=0;delay=0;endendcaseendassign count=delay;assign counting=state==cnt;assign done=state==waitter;endmodule

结果正确:

本题结合前面的FSM，为一个较为完整的计数器。